Monday, November 13, 2017

Gettering Explained!

Gettering


  • Gettering is defined as the process of removing device-degrading impurities from the active circuit regions of the wafer.
  • Gettering, which can be performed during crystal growth or in subsequent wafer fabrication steps, is an important ingredient for enhancing the yield of VLSI manufacturing.
  • The general mechanism by which gettering removes impurities from device regions may be described by the following steps: 
  • The impurities to be gettered are released into solid solution from whatever precipitate they're in;
  • They undergo diffusion through the silicon;
  • They are trapped by defects such as dislocations or precipitates in an area away from device regions.
  • There are two general classifications of gettering, namely, extrinsic, and intrinsic.

  1. Extrinsic gettering: refers to gettering that employs external means to create the damage or stress in the silicon lattice in such a way that extended defects needed for trapping impurities are formed.  These chemically reactive trapping sites are usually located on the wafer backside.
  2. Intrinsic gettering: refers to gettering that involves impurity trapping sites created by precipitating supersaturated oxygen out of the silicon wafer.  The precipitation of supersaturated oxygen creates clusters that continuously grow, introducing stress to the wafer as this happens.


The advantages of intrinsic gettering over extrinsic gettering are:
  1. It does not require subjecting the wafer to any treatment except for heating; 
  2. Its volume of impurity sink is significantly larger than that of external gettering on the wafer backside;
  3. Its gettering regions are much closer to the device regions.


For ICs, the primary unwanted impurities are metals, which:
Increase Recombination
  • -       Increase junction leakage.
  • -       Reduce lifetimes.
  • -       Reduces efficiency of solar cells and DRAMs.
  • -       Reduces beta in BJTs.

Segregate to interfaces resulting in interface states:
  • -       Noise
  • -       Threshold voltage shifts by trapping charges.
  • -       Degraded Si/SiO2 interface.
Precipitates:
  • -       Alternative conducting paths.

Sources of unwanted impurities include:
  • -       Initial melt.
  • -       Chemicals used in processes like cleaning, etching, and the photoresist material.
  • -       Handling – wafer tracks, tweezers, boxes, and particles.
  • -       Process chambers like stainless steel and quartz.

Important note:

Gettering has to be stable over the entire process.

Modeling Wafer Cleaning:

  • Cleaning involves removing particles, organics (photoresist) and metals from wafer surfaces.
  • Particles are largely removed by ultrasonic agitation during cleaning.
  • Organics like photoresists are removed in O2 plasma or in H2SO4/H2O2 solutions.
  • The “RCA clean” is used to remove metals and any remaining organics.
  • Metal cleaning can be understood in terms of the following chemistry.
  • Si + 2H 2O « SiO2 + 4H + + 4e – (1)
  • M « M z + + ze – (2)
  • If we have a water solution with a Si wafer and metal atoms and ions, the stronger reaction will dominate.
  • Generally (2) is driven to the left and (1) to the right so that SiO2 is formed and M plates out on the wafer.
  • Good cleaning solutions drive (2) to the right since M+ is soluble and will be desorbed from the wafer surface.
  • The strongest oxidants are at the bottom (H2O2 and O3). These reactions go to the left grabbing e- and forcing (2) to the right.
  • Fundamentally the RCA clean works by using H2O2 as a strong oxidant.

Summary of Key Ideas:

  • A three-tiered approach is used to minimize contamination in wafer processing.
  • Particle control, wafer cleaning and gettering are some of the "nuts and bolts" of chip manufacturing.
  • The economic success (i.e. chip yields) of companies manufacturing chips today depends on careful attention to these issues.
  1. Level 1 control - clean factories through air filtration and highly purified chemicals and gases.
  2. Level 2 control - wafer cleaning using basic chemistry to remove unwanted elements from wafer surfaces.
  3. Level 3 control - gettering to collect metal atoms in regions of the wafer far away from active devices.
  4. The bottom line is chip yield. Since "bad" die are manufactured alongside "good" die, increasing yield leads to better profitability in manufacturing chips.


  ~Jay Mehta
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Jay Mehta.
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