The Novice Writer: Design Rules Explained!

Design Rules

CMOS Inverter Circuit.

Design rules are a set of geometrical specifications that dictate the design of the layout
The layout is a top view of a chip.
Design process is aided by stick diagram and layout
Stick diagram gives the placement of different components and their connection details
But the dimensions of devices are not mentioned
Circuit design with all dimensions is Layout
Fabrication process needs different masks, these masks are prepared from layout
Layout is an Interface between circuit designer and fabrication engineer
The layout is made using a set of design rules.
Design rules allow translation of circuit (usually in stick diagram or symbolic form) into actual geometry in silicon wafer
These rules usually specify the minimum allowable line widths for physical objects on-chip.
Example: metal, poly-silicon, interconnects, diffusion areas, minimum feature dimensions, and minimum allowable separations between two such features.

The need for Design Rules:

Better area efficiency
Better Yield
Better reliability
Increase the probability of fabricating a successful product on Si wafer

Color Code:

Dry Oxidation – Light Grey

Wet Oxidation – Dark Grey

N – Well – Light Green

P – Well – Brown

N+ Region or Diffusion – Dark Green

P+ Region or Diffusion – Yellow

Implant – Yellow

Poly- Silicon – Red

Metal 1 – Blue

Metal 2 – Purple

Contacts or Via – Black

Stick Diagrams:

A stick diagram is a symbolic representation of a layout.
In stick diagram, each conductive layer is represented by a line of distinct color.
A width of the line is not important, as stick diagrams just give only wiring and routing information.
Shows all the components and contacts in their relative placement.
Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.
Poly crosses diffusion forms transistor.
Normally, the first step is to draw two parallel metal (blue) VDD and GND rails.
There should be enough space between them for another circuit elements.
Draw Demarcation line (Brown) at the center of VDD and GND rails.
This line represents the well (n/p-well).
Next, Active (Green/yellow) paths must be drawn for requiredPU & PD transistors above & below DL.
Draw vertical poly crossing both diffusions (Green & yellow)
Remember, Poly (Red) crosses Active (Green/yellow), where
the transistor is required.
No Diffusion can cross demarcation line.
Only poly and metal can cross demarcation line.
N-diffusion and p-diffusion are joined using a metal wire.
Place all PMOS above and NMOS below demarcation line.
Connect them using wires (metal).
Blue may cross over red or green, without the connection.
The connection between layers is specified with X.
Metal lines on the different layer can cross one another, connections are done using via.

Types of Design Rule:

Industry Standard: Micron Rule

All device dimensions are expressed in terms of absolute dimension(μm/nm)
These rules will not support proportional scaling

λ Based Design Rules :

Developed by Mead and Conway.
All device dimensions are expressed in terms of a scalable parameter λ.
λ = L/2; L = The minimum feature size of transistor
L = 2 λ
These rules support proportional scaling.
They should be applied carefully in sub-micron CMOS process.
Minimum length or width of a feature on a layer is 2λ
To allow for shape contraction
Minimum separation of features on a layer is 2λ
To ensure adequate continuity of the
intervening materials.
Two Features of different mask layers can be misaligned by a maximum of 2λ on the wafer.
If the overlap of these two different mask layers can be catastrophic to the design, they must be separated by at least 2λ
If the overlap is just undesirable, they must be separated by at least λ.

Line size and spacing:

metal1:

Minimum width=3λ, Minimum Spacing=3λ

metal2:

Minimum width=3λ, Minimum Spacing=4λ

poly:

Minimum width= 2λ, Minimum Spacing=2λ

ndiff/pdiff:

Minimum width= 3λ, Minimum Spacing=3λ,

wells:

minimum width=6λ,
minimum n-well/p-well space = 6λ( They are at same potential); = 9λ (They are at different potential)

Transistors:

Min width=3λ
Min length=2λ
Min poly overhang=2λ

Contacts (Vias)

Cut size: exactly 2λ X 2λ
Cut separation: minimum 2λ
Overlap: min 1λ in all directions

Metal connects to polySi/diffusion by contact cut.Contact area: 2λ *2λ
Metal and polySi or diffusion must overlap this contact area by λ so that the two desired conductors encompass the contact area despite any misalignment between conducting layers and the contact hole.