The Novice Writer: Design Methodologies

Design Methodologies:

Two types:

Full custom design
Semi-custom design: Standard Cell, Gate Array, and Programmable Logic Device (PLD)

Full Custom Design:

In this method of designing, designer designs each of the following parts of transistor individually:

The geometry
The orientation
The placement

The throughput of the device via this method is low.
Level of creativity is high.
Design productivity is low.
The entire mask needs to be produced without using any libraries.
The development cost of the design is prohibitively high.
Thus, the concept of reuse of the designs by using libraries is becoming popular.

Semi-Custom Design:

In this method of designing, both cost and time are drastically reduced but the quality of performance is not comparable to that of Full Custom Design.

Standard Cell:

In this design style, all of the commonly used logic cells are developed, characterized, and stored in a standard cell library.
This library includes:

Inverters
NAND gates
NOR gates
Complex AOIs/OAIs
D – Latches
Flip Flops
Counters

Each type can be implemented in several versions to provide the adequate driving capability.
Designer sends the schematic to the fabricator who then designs the mask.
Larger the library, more the cost.
Standard Cell approach guarantees the working of the device.
Advantages:

Sophisticated systems can be built
Less routing area
Improved speed
More compact
Flexible to include digital and analog functions

Disadvantages:

Mask cost

Gate Array:

In this design style, the circuit is prefabricated with no particular function in which transistors and other devices are placed unconnected at regular predefined positions and manufactured on the wafer.
The only mask that needs to be created is that of metallization.
Advantages:

Reduced mask cost
Fewer custom mask needs to be produced
Higher Throughput
Less time to market
Fastest logic implementation is done compared to the above two.

Disadvantages:

Size is fixed
Numbers of transistors are fixed
Low efficiency
Most of the transistors may not be used
Suitable for low production volumes only

Programmable Logic Devices (PLDs):

These are the ICs, that can be programmed as per user’s specifications.
Programmable logic devices have an undefined function at the time of manufacture and it behaves in the desired manner once it is programmed.
PLDs consist of:

Configurable logic
Flip Flops
Programmable interconnects

Application-Specific Integrated Circuits (ASICs):

Using an extensive suite of CAD tools that portray the system design in terms of standard digital logic constructs:

State diagrams, functions tables, and logic diagram
Designer does not need any knowledge of the underlying electronics or the physic of the silicon chip
Major drawback is that all characteristics are set by the architectural design

Regularity:

Decomposition of a large system in simple and similar blocks as much as possible. Example: Design of array structures consisting of identical cells - such as a parallel multiplication array.

Modularity:

Modularity in design means that the various functional blocks, which make up the larger system must have well-defined functions and interfaces.
Modularity allows that each block or module can be designed relatively independently from each other.
All of the blocks can be combined with ease at the end of the design process, to form the large system.
The concept of modularity enables the parallelization of the design process.

Locality:

The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible.

VLSI Design Flow:

The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirements. The initial design is developed and tested against the requirements. When requirements are not met, the design has to be improved. If such improvement is either not possible or too costly, then the revision of requirements and its impact analysis must be considered. The Y-chart (first introduced by D. Gajski) shown in the image below illustrates a design flow for most logic chips, using design activities on three different axes (domains) which resemble the letter Y.

Typical VLSI design flow in three domains (Y-chart representation).

The Y-chart consists of three major domains, namely:

Behavioral domain
Structural domain
Geometrical layout domain

The design flow starts from the algorithm that describes the behavior of the target chip. The corresponding architecture of the processor is first defined. It is mapped onto the chip surface by floor planning. The next design evolution in the behavioral domain defines finite state machines (FSMs) which are structurally implemented with functional modules such as registers and arithmetic logic units (ALUs). These modules are then geometrically placed onto the chip surface using CAD tools for automatic module placement followed by routing, with a goal of minimizing the interconnects area and signal delays. The third evolution starts with a behavioral module description. Individual modules are then implemented with leaf cells. At this stage, the chip is described in terms of logic gates (leaf cells), which can be placed and interconnected by using a cell placement & routing program. The last evolution involves a detailed Boolean description of leaf cells followed by a transistor level implementation of leaf cells and mask generation. In standard-cell based design, leaf cells are already pre-designed and stored in a library for logic design use.

A more simplified view of VLSI design flow.

Above image provides a more simplified view of the VLSI design flow, taking into account the various representations, or abstractions of design - behavioral, logic, circuit and mask layout. Note that the verification of design plays a very important role in every step during this process. The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a later stage, which ultimately increases the time-to-market.

Although the design process has been described in the linear fashion for simplicity, in reality, there are many iterations back and forth, especially between any two neighboring steps, and occasionally even remotely separated pairs. Although top-down design flow provides an excellent design process control, in reality, there is no truly unidirectional top-down design flow. Both top-down and bottom-up approaches have to be combined. For instance, if a chip designer defined an architecture without close estimation of the corresponding chip area, then it is very likely that the resulting chip layout exceeds the area limit of the available technology. In such a case, in order to fit the architecture into the allowable chip area, some functions may have to be removed and the design process must be repeated. Such changes may require significant modification of the original requirements. Thus, it is very important to feed forward low-level information to higher levels (bottom-up) as early as possible.

~Jay Mehta